# ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(118): VHDL Compiler exiting # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(113): Symbol "g_or" has already been declared in this region. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(108): Symbol "g_and_2" has already been declared in this region. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(103): Symbol "g_and_1" has already been declared in this region. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(98): Symbol "g_xor_2" has already been declared in this region. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(93): Symbol "g_xor" has already been declared in this region. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(93): VHDL Compiler exiting # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(90): Indexed name is type (error) expecting type ieee.std_logic_1164.std_logic.
# ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(90): Prefix of indexed name must be an array. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(78): Indexed name is type (error) expecting type ieee.std_logic_1164.std_logic.
# ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(80): Cannot read output "o_c". # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(78): Prefix of indexed name must be an array. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(74): Indexed name is type (error) expecting type ieee.std_logic_1164.std_logic. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(75): Cannot read output "o_c". # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(74): Prefix of indexed name must be an array. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(64): Indexed name is type (error) expecting type ieee.std_logic_1164.std_logic. # ** Error: /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl(64): Prefix of indexed name must be an array. # - Compiling architecture structure of nbit_full_adder # Model Technology ModelSim SE-64 vcom 6.5c Compiler 2009.08 Aug 27 2009 Vcom -reportprogress 300 -work work /home/tstapler/CPRE381/lab2/P1/nbit_full_adder.vhdl # ** Error: Failed to find design unit work.nbit_full_adder. # ** Note: (vsim-3812) Design is being optimized. # vsim -voptargs=+acc work.nbit_full_adder # // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS # // PROPRIETARY INFORMATION WHICH IS THE PROPERTY # // Copyright 1991-2009 Mentor Graphics Corporation